A phase locked loop (PLL) is an essential component of radio frequency (RF) and millimeter wave (mmWave) applications. A high performance PLL is needed to implement the RF and mmWave applications.
In known fractional-N frequency synthesizers for the PLL, an effective frequency divide ratio is a fractional number, which enables a relatively high frequency reference signal to be used to achieve fine resolution of frequencies in synthesizer output signals. This fractional number is typically achieved by periodically changing an integer divide ratio so that a desired fractional number can be approximated.
One typical disadvantage associated with fractional-N frequency synthesis is the generation of unwanted low-frequency “spurs” by a divider. These spurs make fractional-N frequency synthesizers impractical for many applications unless they are suppressed to a negligible level. Further, in fractional-N frequency synthesizers, a sigma-delta modulator is used to generate an average fractional value. However, the sigma-delta modulator also generates unwanted noise.
One challenge of noise cancellation in fractional N-frequency synthesizers is being able to accurately determine an error gain. The error gain is a ratio of the time to digital converter (TDC) gain (i.e., 2*KTDC) to a channel number (i.e., N+Frac). One possible approach to noise cancellation is to measure the TDC gain by measuring a known pulse and then using a sequential divider to compute the ratio. In another possible approach to noise cancellation, a correlator and a low pass filter are used to accurately determine the error gain. However, these approaches for noise cancellation use analog circuitry, are non-adaptive, and/or requires complex circuitry.